1. Field of the Invention
The present invention relates to a method of removing post-etch residues, and more particularly to a method of removing post-etch residues without causing arcs.
2. Description of the Prior Art
Damascene interconnect processes incorporated with copper are known in the art, which are also referred to as “copper damascene processes” in the semiconductor industry. Generally, the copper damascene processes are categorized into single damascene process and dual damascene process. Because the dual damascene has advantages of simplified processes, lower contact resistance between wires and plugs, and improved reliance, it is widely applied in damascene interconnect technique. In addition, to reducing resistance and parasitic capacitance of the multi-level interconnect and improving speed of signal transmission, the dual damascene interconnect in state-of-the-art is fabricated by filling trench or via patterns located in dielectric layer which comprise low-K material with copper and performing a planarization process to obtain a metal interconnect. According to the patterns located in the dielectric layer, the dual damascene process is categorized into trench-first process, via-first process, partial-via-first process, and self-aligned process.
However, when a via or a trench is formed by etching the dielectric layer, lots of charges are accumulated on the dielectric layer. Therefore, when the post-etch residues on the dielectric layer is removed by a cleaning solution, arcs may form when the cleaning solution contacts the surface of the dielectric layer with lots of charges. Then, semiconductive elements below or on the dielectric layer will be cracked because of the arcs.